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ds04-21375-2e fujitsu semiconductor data sheet assp dual serial input pll frequency synthesizer MB15F72UV n n n n description the fujitsu MB15F72UV is a serial input phase locked loop (pll) frequency synthesizer with a 1300 mhz and a 350 mhz prescalers. a 64/65 or a 128/129 for the 1300 mhz prescaler, and a 8/9 or a 16/17 for the 350 mhz prescaler can be selected for the prescaler that enables pulse swallow operation. the bicmos process is used, as a result a supply current is typically 2.5 ma at 2.7 v. the supply voltage range is from 2.4 v to 3.6 v. a refined charge pump supplies well-balanced output current with 1.5 ma and 6 ma selectable by serial data. the data format is the same as the previous one mb15f02sl, mb12f72sp/ul. fast locking is achieved for adopting the new circuit. MB15F72UV is in the new small package (bcc18) , which decreases a mount area of MB15F72UV about 50 % comparing with the former bcc20 (for dual pll) . MB15F72UV is ideally suited for wireless mobile communications, such as cdma. n n n n features ? high frequency operation : rf synthesizer : 1300 mhz max : if synthesizer : 350 mhz max ? low power supply voltage : v cc = 2.4 v to 3.6 v ? ultra low power supply current : i cc = 2.5 ma typ (v cc = 2.7 v, sw if = sw rf = 0, ta = + 25 c, in if, rf locking state) (continued) n n n n pac k ag e 18-pin plastic bcc (lcc-18p-m05)
MB15F72UV 2 (continued) ? direct power saving function : power supply current in power saving mode typ 0.1 m a (v cc = 2.7 v, ta = + 25 c) max 10 m a (v cc = 2.7 v) ? software selectable charge pump current : 1.5 ma/6.0 ma typ ? dual modulus prescaler : 1300 mhz prescaler (64/65 or 128/129 ) /350 mhz prescaler (8/9 or 16/17) ? 23 bit shift resister ? serial input 14-bit programmable reference divider : r = 3 to 16,383 ? serial input programmable divider consisting of : - binary 7-bit swallow counter : 0 to 127 - binary 11-bit programmable counter : 3 to 2,047 ?on - chip phase control for phase comparator ?on - chip phase comparator for fast lock and low noise ? built-in digital locking detector circuit to detect pll locking and unlocking. ? operating temperature : ta = - 40 c to + 85 c ? serial data format compatible with mb15f72ul ? ultra small package bcc18 (2.4 mm 2.7 mm 0.45 mm)
MB15F72UV 3 n n n n pin assignments 1 2 3 4 5 6 7 8 9 16 18 17 gnd rf le fin rf v ccrf do rf xfin rf osc in ld/fout ps rf data clock 10 11 12 13 14 15 gnd if gnd fin if v ccif do if xfin if ps if (bcc-18) top view (lcc-18p-m05)
MB15F72UV 4 n n n n pin description pin no. pin name i/o descriptions bcc 1gnd ? ground for osc input buffer and the shift register circuit. 2fin if i prescaler input pin for the if-pll. connection to an external vco should be via ac coupling. 3xfin if i prescaler complimentary input pin for the if-pll section. this pin should be grounded via a capacitor. 4gnd if ? ground for the if-pll section. 5v ccif ? power supply voltage input pin for the if-pll section, the osc input buffer and the shift register circuit. 6d oif o charge pump output pin for the if-pll section. 7ps if i power saving mode control for the if-pll section. this pin must be set at l when the power supply is started up. (open is prohibited.) ps if = h ; normal mode / ps if = l ; power saving mode 8ld/fouto lock detect signal output (ld) /phase comparator monitoring output (fout) pins.the output signal is selected by lds bit in the serial data. lds bit = h ; outputs fout signal / lds bit = l ; outputs ld signal 9ps rf i power saving mode control pin for the rf-pll section. this pin must be set at l when the power supply is started up. (open is prohibited.) ps rf = h ; normal mode / ps rf = l ; power saving mode 10 d orf o charge pump output pin for the rf-pll section. 11 v ccrf ? power supply voltage input pin for the rf-pll section 12 gnd rf ? ground for the rf-pll section 13 xfin rf i prescaler complimentary input pin for the rf-pll section. this pin should be grounded via a capacitor. 14 fin rf i prescaler input pin for the rf-pll. connection to an external vco should be via ac coupling. 15 le i load enable signal input pin (with the schmitt trigger circuit) when le is set h, data in the shift register is transferred to the corresponding latch according to the control bit in the serial data. 16 data i serial data input pin (with the schmitt trigger circuit) data is transferred to the corresponding latch (if-ref. counter, if-prog. counter, rf-ref. counter, rf-prog. counter) according to the control bit in the serial data. 17 clock i clock input pin for the 23-bit shift register (with the schmitt trigger circuit) one bit of data is shifted into the shift register on a rising edge of the clock. 18 osc in i the programmable reference divider input. tcxo should be connected with an ac coupling capacitor.
MB15F72UV 5 n n n n block diagram clock data le ps rf xfin rf fin rf osc in fin if ps if v ccif gnd if fp if do if ld if t1 t2 t1 t2 fc rf sw rf lds do rf or ld / fout ld fr if fr rf fp if fp rf fr if fr rf fp rf c n 1 c n 2 and v ccrf gnd rf 5 4 6 8 10 12 gnd 1 11 17 16 15 9 13 14 18 2 xfin if 3 7 intermittent mode control (if-pll) prescaler (if-pll) (8/9, 16/17 7 bit latch 11 bit latch binary 7-bit swallow counter (if-pll) binary 11-bit programmable counter (if-pll) phase comp. (if-pll) charge pump (if-pll) current switch 2 bit latch 14 bit latch 1 bit latch binary 14-bit pro- grammable ref. counter(if-pll) c/p setting counter lock det. (if-pll) 2 bit latch 14 bit latch 1 bit latch binary 14-bit pro- grammable ref. counter (rf-pll)) c/p setting counter selector prescaler (rf-pll) (64/65, 128/129) lock det. (rf-pll) intermittent mode control (rf-pll) 3 bit latch fc if sw if lds 3 bit latch 7 bit latch 11 bit latch binary 7-bit swallow counter (rf-pll) binary 11-bit programmable counter (rf-pll) phase comp. (rf-pll) fast lock tuning charge pump (rf-pll) current switch schmitt circuit latch selector schmitt circuit schmitt circuit 23-bit shift register fast lock tuning ld rf
MB15F72UV 6 n n n n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions notes : v ccrf and v ccif must supply equal voltage. even if either rf-pll or if-pll is not used, power must be supplied to v ccrf , and v ccif to keep them equal. it is recommended that the non-use pll is controlled by power saving function. although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection, observe the following precautions when handling the device. when storing and transporting the device, put it in a conductive case. before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. use a conductive sheet on working bench. before fitting the device into or removing it from the socket, turn the power supply off. when handling (such as transporting) the device mounted board, protect the leads with a conductive sheet. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max power supply voltage v cc - 0.5 4.0 v input voltage v i - 0.5 v cc + 0.5 v output voltage ld/fout v o gnd v cc v do if , do rf v do gnd v cc v storage temperature tstg - 55 + 125 c parameter symbol value unit remarks min typ max power supply voltage v cc 2.4 2.7 3.6 v v ccrf = v ccif input voltage v i gnd ? v cc v operating temperature ta - 40 ?+ 85 c
MB15F72UV 7 n n n n electrical characteristics (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) (continued) parameter sym- bol condition value unit min typ max power supply current i ccif * 1 fin if = 270 mhz, v ccif = vp if = 2.7 v 0.6 1.0 1.4 ma i ccrf * 1 fin rf = 910 mhz, v ccrf = vp rf = 2.7 v 1.0 1.5 2.1 ma power saving current i psif ps if = ps rf = l ? 0.1 * 2 10 m a i psrf ps if = ps rf = l ? 0.1 * 2 10 m a operating frequency fin if * 3 fin if if pll 50 ? 350 mhz fin rf * 3 fin rf rf pll 100 ? 1300 mhz osc in f osc ? 3 ? 40 mhz input sensitivity fin if pfin if if pll, 50 w system - 15 ?+ 2dbm fin rf pfin rf rf pll, 50 w system - 15 ?+ 2dbm osc in v osc ? 0.5 ? v cc v p - p h level input voltage data, le, clock v ih schmitt trigger input 0.7 v cc + 0.4 ?? v l level input voltage v il schmitt trigger input ?? 0.3 v cc - 0.4 v h level input voltage ps if , ps rf v ih ? 0.7 v cc ?? v l level input voltage v il ??? 0.3 v cc v h level input current data, le, clock, ps if , ps rf i ih * 4 ?- 1.0 ?+ 1.0 m a l level input current i il * 4 ?- 1.0 ?+ 1.0 m a h level input current osc in i ih ? 0 ?+ 100 m a l level input current i il * 4 ?- 100 ? 0 m a h level output voltage ld/fout v oh v cc = 2.7 v, i oh = - 1 ma v cc - 0.4 ?? v l level output voltage v ol v cc = 2.7 v, i ol = 1 ma ?? 0.4 v h level output voltage do if , do rf v doh v cc = 2.7 v, i doh = - 0.5 ma v cc - 0.4 ?? v l level output voltage v dol v cc = 2.7 v, i dol = 0.5 ma ?? 0.4 v high impedance cutoff current do if , do rf i off v cc = 2.7 v, v off = 0.5 v to v cc - 0.5 v ?? 2.5 na h level output current ld/fout i oh * 4 v cc = 2.7 v ??- 1.0 ma l level output current i ol v cc = 2.7 v 1.0 ?? ma
MB15F72UV 8 (continued) (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) *1 : conditions ; fosc = 12.8 mhz, ta = + 25 c, sw = 0 in locking state. *2 : v ccif = v ccrf = 2.7 v, fosc = 12.8 mhz, ta = + 25 c, in power saving mode ps if = ps rf = gnd, v ih = v cc v il = gnd (at clk, data, le) *3 : ac coupling. 1000 pf capacitor is connected under the condition of minimum operating frequency. *4 : the symbol C (minus) means the direction of current flow. *5 : v cc = 2.7 v, ta = + 25 c (||i 3 | - |i 4 ||) / [ (|i 3 | + |i 4 |) / 2] 100 ( % ) *6 : v cc = 2.7 v, ta = + 25 c [ (||i 2 | - |i 1 ||) / 2] / [ (|i 1 | + |i 2 |) / 2] 100 ( % ) (applied to both l dol and l doh ) *7 : v cc = 2.7 v, [||i do ( + 85 c) | - |i do (C40 c) || / 2] / [|i do ( + 85 c) | + |i do (C40 c) | / 2] 100 ( % ) (applied to both i dol and i doh ) *8 : when charge pump current is measured, set lds = 0 , t1 = 0 and t2 = 1. parameter symbol condition value unit min typ max h level output current do if * 8 do rf i doh * 4 v cc = 2.7 v, v doh = v cc / 2, ta = + 25 c cs bit = 1 - 8.2 - 6.0 - 4.1 ma cs bit = 0 - 2.2 - 1.5 - 0.8 ma l level output current do if * 8 do rf i dol v cc = 2.7 v, v dol = v cc / 2, ta = + 25 c cs bit = 1 4.1 6.0 8.2 ma cs bit = 0 0.8 1.5 2.2 ma charge pump current rate i dol /i doh i domt * 5 v do = v cc / 2 ? 3 ?% vs. v do i dovd * 6 0.5 v v do v cc - 0.5 v ? 10 ?% vs.ta i dota * 7 - 40 c ta + 85 c, v do = v cc / 2 ? 5 ?% i 1 i 1 i 3 i 2 i 4 i dol i doh 0.5 v cc / 2 v cc v cc - 0.5 charge pump output voltage (v)
MB15F72UV 9 n n n n functional description 1. pulse swallow function : f vco = [ (p n) + a] f osc ? r f vco : output frequency of external voltage controlled oscillator (vco) p : preset divide ratio of dual modulus prescaler (8 or 16 for if-pll, 64 or 128 for rf-pll) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127, a < n) f osc : reference oscillation frequency (osc in input frequency) r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) 2. serial data input the serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of if/ rf-pll sections, and programmable reference dividers of if/rf-pll sections are controlled individually. the serial data of binary data is entered through data pin. on a rising edge of clock, one bit of the serial data is transferred into the shift register. on a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. (1) shift register configuration the programmable reference counter for the if-pll the programmable reference counter for the rf-pll the programmable counter and the swallow counter for the if-pll the programmable counter and the swallow counter for the rf-pll cn1 0 1 0 1 cn2 0 0 1 1 (lsb) (msb) data flow ? programmable reference counter note : data input with msb first. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cn1 cn2 t1 t2 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 cs x x x x cs : charge pump current select bit r1 to r14 : divide ratio setting bits for the programmable reference counter (3 to 16,383) t1, t2 : ld/fout output setting bit. cn1, cn2 : control bit x : dummy bits (set 0 or 1)
MB15F72UV 10 (2) data setting ? binary 14-bit programmable reference counter data setting (r1 to r14) note : divide ratio less than 3 is prohibited. ? binary 11-bit programmable counter data setting (n1 to n11) note : divide ratio less than 3 is prohibited. ? binary 7-bit swallow counter data setting (a1 to a7) divide ratio r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 300000000000011 4 16383 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratio n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 300000000011 4 2047 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratioa7 a6a5a4a3a2a1 0 0 000000 1 127 0 1 0 1 0 1 0 1 0 1 0 1 1 1 (lsb) (msb) data flow ? programmable counter note : data input with msb first. a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) n1 to n11 : divide ratio setting bits for the programmable counter (3 to 2,047) lds : ld/fout signal select bit sw if / rf : divide ratio setting bit for the prescaler (if : sw if , rf : sw rf ) fc if / rf : phase control bit for the phase detector (if : fc if , rf : fc rf ) cn1, cn2 : control bit 1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23 cn1 cn2 lds sw if / rf fc if / rf a1 a2 a3 a4 a5 a6 a7 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11
MB15F72UV 11 ? prescaler data setting (sw) ? charge pump current setting (cs) ? ld/fout output selectable bit setting ? phase comparator phase switching data setting (fc if , fc rf ) z : high-impedance depending upon the vco and lpf polarity, fc bit should be set. divide ratio sw = = = = 1 sw = = = = 0 prescaler divide ratio if-pll 8/9 16/17 prescaler divide ratio rf-pll 64/65 128/129 current value cs 6.0 ma 1 1.5 ma 0 ld/fout pin state lds t1 t2 ld output 000 010 011 fout outputs fr if 100 fr rf 110 fp if 101 fp rf 111 phase comparator input fc if = = = = 1 fc rf = = = = 1 fc if = = = = 0 fc rf = = = = 0 do if do rf do if do rf fr > fp h l fr < fp l h fr = fp z z (1) (2) high vco output frequency lpf output voltage max (1) vco polarity fc = 1 (2) vco polarity fc = 0 note : give attention to the polarity for using active type lpf.
MB15F72UV 12 3. power saving mode (intermittent mode control circuit) the intermittent mode control circuit reduces the pll power consumption. by setting the ps pins low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pins high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. notes : when power (v cc ) is first applied, the device must be in standby mode, ps if = ps rf = low. serial data input are done after the power supply becomes stable, and then the power saving mode is released after completed the data input. status ps if /ps rf pins normal mode h power saving mode l on off v cc clock data le ps if ps rf (1) (2) (3) t v 1 s t ps > 100 ns (1) ps if = ps rf = l (power saving mode) at power-on (2) set serial data at least 1 m s after the power supply becomes stable (v cc 3 2.2 v) . (3) release power saving mode (ps if , ps rf : l ? h) at least 100 ns after setting serial data.
MB15F72UV 13 4. serial data input timing frequency multiplier setting is performed through a serial interface using the data pin, clock pin, and le pin. setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of the le signal. the following diagram shows the data input timing. lsb msb clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 1st data 2nd data control bit invalid data parameter min typ max unit t 1 20 ?? ns t 2 20 ?? ns t 3 30 ?? ns t 4 30 ?? ns parameter min typ max unit t 5 100 ?? ns t 6 20 ?? ns t 7 100 ?? ns note : le should be l when the data is transferred into the shift register.
MB15F72UV 14 n n n n phase comparator output waveform fr if / fr rf fp if / fp rf ld do if / do rf t wu t wl d o if / do rf z h l z h l (fc bit = "1") (fc bit = "0") notes : phase error detection range = - 2 p to + 2 p pulses on do if /do rf signals are output to prevent dead zone during locking state. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu 3 2/fosc : e.g. t wu 3 156.3 ns when fosc = 12.8 mhz t wu 4/fosc : e.g. t wl 312.5 ns when fosc = 12.8 mhz if-pll section rf-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l ? ld output logic
MB15F72UV 15 n n n n test circuit (for measuring input sensitivity fin/osc in ) ld/ fout do if v ccif 1000 pf 0.1 m f 0.1 m f ps if gnd if fin if xfin if gnd osc in do rf v ccrf ps rf gnd rf xfin rf fin rf le data clock s.g. s.g. s.g. 1000 pf 50 w 1000 pf 50 w 1000 pf 50 w 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 MB15F72UV 1000 pf v ccrf note : terminal number shows that of tssop-20. controller (divided ratio setting) oscilloscope
MB15F72UV 16 n n n n typical characteristics 1. fin input sensitivity 10 0 - 10 - 20 - 30 - 40 - 50 0 200 400 600 800 1000 1200 1400 1600 1800 2000 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec fin rf (mhz) pfin rf (dbm) 10 0 - 10 - 20 - 30 - 40 - 50 0 100 200 300 400 500 600 700 800 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec fin if (mhz) pfin if (dbm) rf-pll input sensitivity vs. input frequency if-pll input sensitivity vs. input frequency catalog guaranteed range catalog guaranteed range
MB15F72UV 17 2. osc in input sensitivity 10 0 - 10 - 20 - 30 - 40 - 50 0 50 100 150 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec input sensitivity vs. input frequency input frequency f osc (mhz) input sensitivity v osc (dbm) catalog guaranteed range
MB15F72UV 18 3. rf/if-pll do output current - 0.50 1.0 3.0 0.0 2.0 2.5 1.5 0.5 - 1.00 - 1.50 - 2.00 - 2.50 0.00 0.50 1.00 1.50 2.00 2.50 v cc = 2.7 v, ta = +25?c - 2.00 1.0 3.0 0.0 2.0 2.5 1.5 0.5 - 4.00 - 6.00 - 8.00 0.00 2.00 4.00 6.00 8.00 v cc = 2.7 v, ta = +25?c i do - v do charge pump output current i do (ma) charge pump output voltage v do (v) i do - v do charge pump output current i do (ma) ? 1.5 ma mode ? 6.0 ma mode charge pump output voltage v do (v)
MB15F72UV 19 4. fin input impedance 3 2 906.94 w - 1.2097 k w 50 mhz 156.47 w - 588.44 w 150 mhz 65.719 w - 363.31 w 250 mhz 1 : 2 : 3 : center 275.000 000 mhz span 450.000 000 mhz 4 4 : 39.5 w- 258.98 w 1.7558 pf 350.000 000 mhz 1 30.711 w - 221.73 w 400 mhz 16.602 w - 120.77 w 700 mhz 12.367 w - 76.926 w 1 ghz 1 : 2 : 3 : start 100.000 000 mhz stop 1 500.000 000 mhz 4 : 10.426 w- 50.781 w 2.4109 pf 1 300.000 000 mhz 1 3 2 4 fin if input impedance fin rf input impedance
MB15F72UV 20 5. osc in input impedance 1 2 3 882 w - 5.1865 k w 10 mhz 257.13 w - 2.6638 k w 20 mhz 121.69 w - 1.7799 k w 30 mhz 1 : 2 : 3 : start 3.000 000 mhz stop 40.000 000 mhz 4 4 : 074.81 w- 1.3334 k w 2.9839 pf 40.000 000 mhz osc in input impedance
MB15F72UV 21 n n n n reference information ( for lock - up time , phase noise and reference leakage ) (continued) atten 10 db rl 0 dbm center 738.5000 mhz rbw 1.0 khz vbw 1.0 khz span 200.0 khz swp 500 ms d mkr - 70.00 db 12.3 khz vavg 16 10 db/ d mkr 12.3 khz - 70.00 db * atten 10 db rl 0 dbm center 738.50000 mhz rbw 30 hz vbw 30 hz span 10.00 khz swp 1.92 s d mkr - 58.16 db 1.00 khz vavg 16 10 db/ d mkr 1.00 khz - 58.16 db * s.g. osc in fin vco d o lpf test circuit spectrum analyzer 3 k w 56000 pf 8.2 k w 5600 pf 3900 pf f vco = 738.5 mhz k v = 30 mhz/v fr = 12.5 khz f osc = 19.8 mhz lpf v cc = 2.7 v v vco = 3.75 v ta = + 25 c cp : 6 ma mode ? pll reference leakage ? pll phase noise
MB15F72UV 22 (continued) 0.00 s 5.000 ms 1.000 ms/div 10.00 ms 775.504000 mhz 775.500000 mhz 775.496000 mhz t 1 533 m st 2 3.800 m s d 3.267 ms 0.00 s 5.000 ms 1.000 ms/div 10.00 ms t 1 533 m st 2 3.733 m s d 3.200 ms 738.504000 mhz 738.500000 mhz 738.496000 mhz ? pll lock up time ? pll lock up time 738.5 mhz ? 775.5 mhz within 1 khz lch ? hch 3.267 ms 775.5 mhz ? 738.5 mhz within 1 khz hch ? lch 3.2 ms
MB15F72UV 23 n n n n application example ld/ fout do if v ccif 1000 pf 0.1 m f 0.1 m f ps if gnd if fin if xfin if gnd osc in do rf v ccrf ps rf gnd rf xfin rf fin rf le data clock 1000 pf 1000 pf 1000 pf 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 MB15F72UV 1000 pf v ccrf lock detect output vco lpf vco lpf output tcxo v ccif note : clock, data, le : the schmitt trigger circuit is provided (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input) . controller (divided ratio setting)
MB15F72UV 24 n n n n usage precautions (1) v ccrf and v ccif must be equal voltage. even if either rf-pll or if-pll is not used, power must be supplied to v ccrf and v ccif to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions : -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. n n n n ordering information part number package remarks MB15F72UVpvb 18-pin plastic bcc (lcc-18p-m05)
MB15F72UV 25 n n n n package dimension 18-pin plastic bcc (lcc-18p-m05) dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited c18058s-c-1-1 0.05(.002) 1 2.70 0.10 2.40 0.10 (.094 .004) 0.45 0.05 0.075 0.025 (.003 .001) (.018 .002) (stand off) 0.45(.018) typ. 2.31(.090) 1.90(.075) ref 2.01(.079) typ typ. 0.45(.018) 1.35(.053) 2.28(.090) "a" "b" "c" 15 10 6 6 1 15 10 0.28 0.06 (.011 .002) 0.36 0.06 (.014 .002) c0.10(.004) 0.25 0.06 (.010 .002) 0.25 0.06 (.010 .002) details of "b" part details of "c" part details of "a" part (.106 .004) ref ref typ index area min. 0.14(.006) (mount height) (.011 .002) 0.28 0.06 (.014 .002) 0.36 0.06 0.90(.035) ref
MB15F72UV fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0312 ? fujitsu limited printed in japan

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